Basics of Digital Circuits

1. Basics of Digital Circuits

2. Levels of Design Abstraction

System
Register-Transfer
Add
Accumulator
Input
Command Register
+1
Command Counter
&
&
Gate
1
J TT
C
K
Circuit
Device
n+
p+
n
n+
p

3. Combinational and Sequential Logic Circuits

In
Logic circuit
In
Logic circuit
Out
Out
State
(a) Combinational
Output = f(In)
(b) Sequential
Output = f(In, Previous In)

4. Classification of CMOS Digital Circuits

CMOS Digital
Circuits
Static Logic
Circuits
Dynamic
Logic Circuits
At any time, except switching moment, static circuit output is connected either to
VDD, or VSS through a small resistance
Static circuit output always takes logic function value (except switching time
transition process)
In a dynamic circuit the output signal value is conditioned by the charge present
on the high impedance nodes

5. Properties of Logic Functions (2)

-a&0=0
-a+0=a
-a&1=a
-a+1=1
-a&a=a
- a + a =a
-a&a=0
-a+a=1
-a 0=a
-a 1=a
-a a=0
-a a=1
-a b=a b=a b=a b 1

6. Combinational Logic Cells

• Inverter
y=x
y
x
1
1
0
0
• AND
x1
x2
x
y
0
1
1
0
• OR
y
y = x1 & x 2 = x1 x 2
x1
x1
x2
y
x2
0
0
0
y
y = x1 + x 2
x1
x2
y
0
0
0
0
1
0
0
1
1
1
0
0
1
0
1
1
1
1
1
1
1

7. Propagation Delay

X
x
y
100%
50%
y
t10
t01
t
100%
t 01 + t10 t P LH + t PHL
t pd =
=
2
2
50%
t

8. 2 Input NAND Circuit

VDD
M3
M4
A
M2
B
M1
In case of N inputs
W3+W4=2Wp
3+ 4=2 p
L1+L2=2Ln , 1 2/( 1+ 2)= n/2
AB
Transconductance ratio
= n/4 p
VSP =
n
Vtn + (VDD − Vtp )
4 p
1+
VSP =
n
4 p
n
Vtn + (VDD − Vtp )
N 2 p
1+
n
N 2 p

9. 2 Input NOR Circuit

VDD
A
Transconductance ratio=4 n/ p
M3
A+B
M1
M1
In case of N inputs
1+ 2=2 n
L3+L4=2Lp , 3 4/( 3+ 4)= p/2
M4
B
W1+W2=2Wn
VSP =
4 n
Vtn + (VDD − Vtp )
p
1+
VSP =
4 n
p
N 2 n
Vtn + (VDD − Vtp )
p
N 2 n
1+
p

10. Demultiplexer

Y0
S0
Y1
S1
DEMUX
X
DC
Y0
Y1
Yn-1
Sm-1
Yn-1
S0
S1
Sm-1
X
IN

11. Decoder/Demultiplexer

S0
S0 S1 S1 X
&
&
&
&
Y0
Y1
Y2
Y3
X S1 S0
Y0 Y1 Y2 Y3
0
0
0
0 0 0
0
0
0
1
0 0 0
0
0
1
0
0 0 0
0
0
1
1
0 0 0
0
1
0
0
1 0 0
0
1
0
1
0 1 0
0
1
1
0
0 0 1
0
1
1
1
0 0 0
1

12. Multiplexer (1)

DIN0
DIN0
DIN1
DIN1
Y
MUX
DINn-1
DINn-1
S0
S1
S0
S1
Sm-1
Sm-1
MUX
Y

13. Multiplexer (2)

S0
S0 S1 S1 X3 X2 X1 X0
&
&
1
&
&
Y

14. Pass Transistor Gate

D
S
S
D
CL
G
CL charged to
VDD
VDD
G
+
-
CL discharged
S
D
CL
CL
CL charged to
VDD
G
G
D
S
S
tPHL= tPLH=RnCL
S
G
G
D
VDD
G
+
-
CL discharged
G
D
tPHL= tPLH=RpCL
CL

15. Transmission Gate

EN
OUT
IN
CL
IN,
OUT
EN=1
tPHL= tPLH=(Rn||Rp)CL
t

16. Sequential Logic Circuit

FF’s
f
Combinational
tp,comb
Out
• Feedback
• Clock
• Memory
In

17. RS Latch

S
R
S
R
Q
S
Q
R
Q
Q
Q
Q
S
R
Q
Q
0
0
Q
Q
1
0
1
0
0
1
0
1
1
1
0
0
S
R
Q
Q
S
Q
1
1
Q
Q
R
Q
0
1
1
0
1
0
0
1
0
0
1
1

18. Clocked Latch

S
S
Q
C
R
R
C=0 S = R=1, Qn+1 =Qn
Q

19. MS D-Flip Flop

C
C
T2
C
C
D
Q
C
A
C
T4
T1
C
B
C
T3
C
Q