Strategic Viability of Low-Volume SiP Production: Bare-Die Supply-Chain Constraints

1.

Strategic Viability of System-in-Package (SiP)
Technology for Low-Volume Production
An Analysis of the Bare Die Global Supply Chain and Ecosystem Constraints
Candidate
Shukhrat Sultonov · s300657
Supervisors Prof. Luciano Scaltrito · Prof.ssa Valentina Bertana · Prof. Sergio Ferrero · Prof. Emilio Paolucci
MSc Engineering and Management · September 2026

2.

The problem: can a small producer buy the parts?
SiP is proven at millions of units. Nobody asked whether a producer of hundreds can obtain the chips.
A medical, aerospace or specialised industrial company builds hundreds or thousands of units — not
millions. To shrink its product it needs bare dies: unpackaged chips. Every study says the technology
works. None asks whether that company can actually get the dies.
RQ1
Structure
Who controls the supply of
bare dies, and how tightly?
RQ2
Access
What stops a small buyer
getting them — and what
ways in exist?
RQ3
Viability
Given those limits, when does
SiP make technical and
economic sense?
Sections 1.1–1.2 — problem statement and the three research questions.
2

3.

What is a bare die, and what is System-in-Package?
A bare die is a chip without its package. SiP puts several of them, from different makers, into one package.
Foundry
Makes chips to others' designs
TSMC · UMC · GlobalFoundries · X-FAB
IDM
Designs and makes its own chips
Intel · Samsung · STMicroelectronics
Why it is hard. A packaged chip is a catalogue product: you order it
and it arrives. A bare die is work in progress inside someone else's
factory. It is sold to large customers under contract, and often not
sold in unpackaged form at all.
Figure 2.5 (SiP panel) and Sections 2.2–2.4 — the three classes of chip maker.
OSAT
Packages and tests chips
ASE · Amkor · JCET
These three groups are where every bare die must
come from.
3

4.

A €700 bn industry where my sectors are invisible
The market grew 25-fold since 1987. Defence and aerospace is one tenth of one per cent of high-end
packaging.
€ 28.6 bn
800
700
world semiconductor revenue in 1987
600
€ 704 bn
€ billion
500
400
in 2025 — about 25 times larger
300
200
0.1%
2025
2023
2021
2019
2017
2015
2013
2011
2009
2007
2005
2003
2001
1999
1997
1995
1993
1991
1989
0
1987
100
of high-end packaging revenue is
defence and aerospace, and it has
not grown
Figure 2.1 — WSTS data via Statista [9]; Figure 6.1 — Yole packaging revenue.
4

5.

What I built: a register that did not exist
463 organisations, every one of the 195 UN member states checked, and one test that decides entry.
463
195
Figure 3.3 — the 463 organisations of the master register, mapped.
The inclusion test: “Does this organisation touch the flow of unpackaged die
between the wafer and the finished module?”
3
organisations, in 24
categories and 3 tiers
countries assessed one by
one — the outcome
recorded either way
smaller registers built
from FY2024 company
filings: foundries, IDMs,
Italy
Chapter 3, Figures 3.1 and 3.3 — research design and country coverage.
5

6.

Where they are: the makers, and everyone else
The chip makers sit in a handful of places. The supporting ecosystem is spread everywhere — including
where no chips are made.
All 463 organisations
93 makers — 36 foundries, 57 IDMs
370 others — the supporting layer
The comparison. Only 93 of the 463 organisations can actually make a die. The other 370 serve the trade
without being able to supply one. So a country can host test houses, distributors, design services and public
programmes — and still have no source of bare die inside its borders. That gap is exactly where Europe, and
Italy in particular, sits.
Figure 3.3 and the master register — organisations plotted by the location of the recorded site.
6

7.

RQ1 — Who controls the die? First, the foundries
One company holds more than 70% of all disclosed pure-play foundry revenue.
≈ 5,600
concentration index of the segment
≈ 95%
of die-relevant capacity is governed
by about twenty organisations
TSMC alone is more than ten times
the next four firms combined.
Figure 4.6, Table 4.3 — FY2024 filings; euro at ECB 2024 average rates.
7

8.

RQ1 — And the makers that keep their own chips
Less extreme than the foundries, but still only eight firms — and they sell die to almost no one.
Samsung Electronics
61,5 bn
Intel
49,4 bn
SK Hynix
45,2 bn
Micron Technology
23,4 bn
Infineon Technologies
15,0 bn
Texas Instruments
14,9 bn
STMicroelectronics
12,3 bn
NXP Semiconductors
11,7 bn
0
10
20
30
40
50
60
FY2024 disclosed revenue (€ billion)
Figure 4.7 — the eight-firm IDM core
Figures 4.7 and 4.8 — FY2024 filings; Lorenz curves from the same datasets.
70
Figure 4.8 — how unequally revenue is shared inside each layer.
The further a curve bends away from the diagonal, the more one
firm dominates.
8

9.

RQ2 — Six barriers stop a small buyer
Each one blocks on its own. Removing any single barrier does not open the door.
1
The die is not a product
It exists inside someone else's
process, made for a named
customer. It is not in a catalogue.
4
The information is
withheld
The design data needed to use a
bare die is not released. There is
no price list and no market view.
2
The capacity is pre-sold
Minimum orders exist to recover
fixed cost. Large customers pay
years in advance for priority.
5
Handling and
traceability
Minimum handling quantities,
shelf life, and a paper trail that
must survive the whole chain.
3
Tested is not the same
as good
A die that passes on the wafer is
not guaranteed good in a
package. One bad die scraps the
whole module.
6
Export control and
clearance
Defence and aerospace need
approvals and cleared suppliers
that a newcomer does not have.
Table 4.6, Section 4.3 — six barrier classes and their primary evidence.
9

10.

RQ2 — Six ways in, only three open to a newcomer
319 of the 371 route places in the register need a relationship the newcomer does not yet have.
A Strategic partnership
A
148
B
a direct, negotiated relationship with the maker
B Shared-wafer / MPW
87
C
many buyers share one wafer; the normal way to prototype
21
D
C Merchant KGD
a specialist buys, tests and resells known-good die
11
E
D Authorised distribution
20
a franchised distributor breaks the minimum order
F
84
0
50
100
E Trusted supply chain
150
200
organisations serving each route
blue = needs existing standing
orange = open to a newcomer
cleared suppliers inside a defence programme
F Ecosystem entry
design houses and competence centres that open a door
Figure 4.11, Table 4.7 — 371 route assignments in the master register.
10

11.

Italy: strong exactly where it cannot trade
Real capability in research, prototyping and test — and no presence at all on the routes that sell die.
160
148
What Italy has
140
51 organisations, 11 of them large
enough to clear the global threshold
— with genuine strength in probe
cards, test equipment and burn-in
120
100
87
84
80
60
40
20
9
14
0
0
A Strategic
21
B Shared
wafer
11
0
C Merchant D Distribution
die
World register
What Italy lacks
20
0
E Trusted
chain
Italian register
4
F Ecosystem
Zero organisations on all three
routes that actually sell die, and
nothing in 10 of the 24 categories —
the whole merchant die trade is
missing
Figure 5.1, Tables 5.1–5.3 — the Italian register, 51 organisations.
11

12.

RQ3 — Costs punish small runs; machines do not
Chasing the newest process is what makes low volume unaffordable — not the factory equipment.
Cost of designing one chip
€ 13.9 M
on a mature 90 nm
process
versus
€ 508 M
on the newest 3 nm
process
≈ 4%
of the world semiconductor equipment market is
assembly and packaging machinery — €4.5 bn of
€104 bn
A 37-fold increase — paid before a single unit ships, and
spread over however many units you build.
The machinery that assembles SiPs costs less, in a whole year
worldwide, than one company's annual factory budget.
So: target mature, already paid-off processes. Scaling
only pays for products shipping in volumes large enough
to absorb that fixed cost — which these sectors never
reach.
Affordable
Not affordable
Assembly, bonding and
test machines — sold
openly, many suppliers
The bare die — few
suppliers, committed to
others, often not sold
Figures 6.3 and 6.8, Tables 6.4 and 3.6 — design cost and the 2024 SEMI market.
12

13.

So — is low-volume SiP viable?
Yes, conditionally. Five things must all be true at once.
1
Use mature processes
not the newest ones — the design cost there is already paid
off
2
Change channel as it matures
shared wafers to prototype, distributors to pilot, direct for
series
3
Engineer for batch variation
small batches vary; high-volume cooling solutions do not
transfer
4
Own test, outsource volume
the equipment is affordable; the die is the scarce thing
5
Pick dies already qualified
treat qualification as a design input, not an afterthought
Meet all five and the case closes — never by shrinking the high-volume model.
13

14.

What the work adds — and where it stops
A dataset that did not exist, a method anyone can re-run, and a finding about institutions rather than
physics.
The dataset
The method
The finding
463 organisations, 24 categories,
3 tiers, 195 countries assessed.
Reusable, and reproducible from
the filings it cites.
One inclusion test, applied
consistently and written down.
Anyone can check the boundary
or rebuild the register.
Inaccessibility is not a law of
physics. It is built out of contracts,
information and regulation — so it
can be changed.
Where it stops. It describes only what companies disclose;
it is a snapshot frozen in July 2026; and it rests on
documents, not interviews.
Europe's missing layer is not factories. It is the
commercial and legal machinery for trading
die.
Thank you — I welcome your questions
With thanks to Matilde Aronne, Giulio Galfré and Giulia Mossotti of Chilab-ITEM for their guidance throughout this work.
14